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Q186: FIFO Design: We have a fifo which clocks data in at 10mhz and clocks data out at 8mhz. On the input there is only 8 data samples in any order during each 10 clocks. In other words, a 10 input clock window will carry only 8 data samples and the other 2 clocks carry no data (data is scattered in any order). How big does the fifo need to be to avoid data over/under-run.
tags: Intel AMD nVidia ATI Sun HP NationalSemi hardware hw design circuit logic
Q187: We have a circular wheel with half painted black and the other half painted white. There are 2 censors mounted 45 degree apart at the surface of this wheel( not touching the wheel) which give a "1" for black and "0" for white passing under them. Design a circuit to detect which way the wheel is moving. Do not assume any fixed position for start.
tags: Intel AMD nVidia ATI Sun HP NationalSemi hardware hw design circuit logic
Q188: The silicon of a new device has memory leak. When all "0" are written into memory, it reads back all "0" without any problem. When all "1" are written, only 80% of memory cells are read back correctly. What can be possibly the problem with the memory?
tags: Intel AMD nVidia ATI Sun HP NationalSemi hardware hw design circuit logic
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Q186: FIFO Design: We have a fifo which clocks data in at 10mhz and clocks data out at 8mhz. On the input there is only 8 data samples in any order during each 10 clocks. In other words, a 10 input clock window will carry only 8 data samples and the other 2 clocks carry no data (data is scattered in any order). How big does the fifo need to be to avoid data over/under-run.
tags: Intel AMD nVidia ATI Sun HP NationalSemi hardware hw design circuit logic
Q187: We have a circular wheel with half painted black and the other half painted white. There are 2 censors mounted 45 degree apart at the surface of this wheel( not touching the wheel) which give a "1" for black and "0" for white passing under them. Design a circuit to detect which way the wheel is moving. Do not assume any fixed position for start.
tags: Intel AMD nVidia ATI Sun HP NationalSemi hardware hw design circuit logic
Q188: The silicon of a new device has memory leak. When all "0" are written into memory, it reads back all "0" without any problem. When all "1" are written, only 80% of memory cells are read back correctly. What can be possibly the problem with the memory?
tags: Intel AMD nVidia ATI Sun HP NationalSemi hardware hw design circuit logic
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