First page
Next page
Q147: What does the following code do? xor eax,eax mov ebx,data ; your input data mov cl,bits ; number of bits loop: ror ebx,1 rcl eax,1 dec cl jnz loop
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q148: Explain what is DMA?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q149: What is pipelining?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q150: What are superscalar machines and vliw machines?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q151: What is cache?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q152: What is cache coherency and how is it eliminated?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q153: What is write back and write through caches?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q154: What are different pipelining hazards and how are they eliminated.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q155: What are different stages of a pipe?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q156: Explain more about branch prediction in controlling the control hazards
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q157: Give examples of data hazards with pseudo codes.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q158: How do you calculate the number of sets given its way and size in a cache?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q159: How is a block found in a cache?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q160: Scoreboard analysis.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q161: What is miss penalty and give your own ideas to eliminate it.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q162: How do you improve the cache performance.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q163: Different addressing modes.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q164: Computer arithmetic with twos complements.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q165: About hardware and software interrupts.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q166: What is bus contention and how do you eliminate it.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q167: What is aliasing?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q168: What is the difference between a latch and a flip flop?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q169: What is the race around condition? How can it be overcome?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q170: What is the purpose of cache? How is it used?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q171: What are the main issues associated with multiprocessor caches and how might you address them?
tags: Intel AMD nVidia ATI Sun HP hw architecture design
Q172: In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
tags: Intel AMD Sun hardware architecture design
Q173: You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
tags: Intel AMD Sun circuit hardware design logic
Q182: An 8bit ADC with parallel output converts input signal into digital numbers. You have to come up with the idea of a circuit, that finds the maxomum of every 10 numbers at the output of the ADC.
tags: Intel AMD nVidia ATI Sun HP hardware hw design circuit logic
Q183: You have two counters to 16, built from negedge D- FF . First circuit is synchronous and second is "ripple" (cascading). Which circuit has a less propagation delay?
tags: Intel NationalSemi AMD Sun hardware hw design circuit logic
Q184: Design a divide-by-3 counter with equal duty cycle ?
tags: Intel AMD nVidia ATI Sun HP NationalSemi hardware hw design circuit logic
Next page
Q147: What does the following code do? xor eax,eax mov ebx,data ; your input data mov cl,bits ; number of bits loop: ror ebx,1 rcl eax,1 dec cl jnz loop
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q148: Explain what is DMA?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q149: What is pipelining?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q150: What are superscalar machines and vliw machines?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q151: What is cache?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q152: What is cache coherency and how is it eliminated?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q153: What is write back and write through caches?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q154: What are different pipelining hazards and how are they eliminated.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q155: What are different stages of a pipe?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q156: Explain more about branch prediction in controlling the control hazards
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q157: Give examples of data hazards with pseudo codes.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q158: How do you calculate the number of sets given its way and size in a cache?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q159: How is a block found in a cache?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q160: Scoreboard analysis.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q161: What is miss penalty and give your own ideas to eliminate it.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q162: How do you improve the cache performance.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q163: Different addressing modes.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q164: Computer arithmetic with twos complements.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q165: About hardware and software interrupts.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q166: What is bus contention and how do you eliminate it.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q167: What is aliasing?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q168: What is the difference between a latch and a flip flop?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q169: What is the race around condition? How can it be overcome?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q170: What is the purpose of cache? How is it used?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q171: What are the main issues associated with multiprocessor caches and how might you address them?
tags: Intel AMD nVidia ATI Sun HP hw architecture design
Q172: In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
tags: Intel AMD Sun hardware architecture design
Q173: You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
tags: Intel AMD Sun circuit hardware design logic
Q182: An 8bit ADC with parallel output converts input signal into digital numbers. You have to come up with the idea of a circuit, that finds the maxomum of every 10 numbers at the output of the ADC.
tags: Intel AMD nVidia ATI Sun HP hardware hw design circuit logic
Q183: You have two counters to 16, built from negedge D- FF . First circuit is synchronous and second is "ripple" (cascading). Which circuit has a less propagation delay?
tags: Intel NationalSemi AMD Sun hardware hw design circuit logic
Q184: Design a divide-by-3 counter with equal duty cycle ?
tags: Intel AMD nVidia ATI Sun HP NationalSemi hardware hw design circuit logic
Next page
