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Q38: What are the different ways to implement a condition where the value of x can be either a 0 or a 1. Apparently the if then else solution has a jump when written out in assembly. if (x == 0) y=a else y=b There is a logical, arithmetic and a data structure solution to the above problem.
tags: microsoft sw programming hw
Q42: I was given two lines of assembly code which found the absolute value of a number stored in twos complement form. I had to recognize what the code was doing. Pretty simple if you know some assembly and some fundamentals on number representation.
tags: microsoft sw programming hw
Q85: Given 3 lines of assembly code : Find what it is doing. cwd xor ax, dx sub ax, dx
tags: microsoft sw programming assembly hw
Q105: Write a program to find whether a given m/c is big-endian or little-endian!
tags: microsoft sw programming hw
Q147: What does the following code do? xor eax,eax mov ebx,data ; your input data mov cl,bits ; number of bits loop: ror ebx,1 rcl eax,1 dec cl jnz loop
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q148: Explain what is DMA?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q149: What is pipelining?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q150: What are superscalar machines and vliw machines?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q151: What is cache?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q152: What is cache coherency and how is it eliminated?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q153: What is write back and write through caches?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q154: What are different pipelining hazards and how are they eliminated.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q155: What are different stages of a pipe?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q156: Explain more about branch prediction in controlling the control hazards
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q157: Give examples of data hazards with pseudo codes.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q158: How do you calculate the number of sets given its way and size in a cache?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q159: How is a block found in a cache?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q160: Scoreboard analysis.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q161: What is miss penalty and give your own ideas to eliminate it.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q162: How do you improve the cache performance.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q163: Different addressing modes.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q164: Computer arithmetic with twos complements.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q165: About hardware and software interrupts.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q166: What is bus contention and how do you eliminate it.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q167: What is aliasing?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q168: What is the difference between a latch and a flip flop?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q169: What is the race around condition? How can it be overcome?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q170: What is the purpose of cache? How is it used?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q171: What are the main issues associated with multiprocessor caches and how might you address them?
tags: Intel AMD nVidia ATI Sun HP hw architecture design
Q182: An 8bit ADC with parallel output converts input signal into digital numbers. You have to come up with the idea of a circuit, that finds the maxomum of every 10 numbers at the output of the ADC.
tags: Intel AMD nVidia ATI Sun HP hardware hw design circuit logic
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Q38: What are the different ways to implement a condition where the value of x can be either a 0 or a 1. Apparently the if then else solution has a jump when written out in assembly. if (x == 0) y=a else y=b There is a logical, arithmetic and a data structure solution to the above problem.
tags: microsoft sw programming hw
Q42: I was given two lines of assembly code which found the absolute value of a number stored in twos complement form. I had to recognize what the code was doing. Pretty simple if you know some assembly and some fundamentals on number representation.
tags: microsoft sw programming hw
Q85: Given 3 lines of assembly code : Find what it is doing. cwd xor ax, dx sub ax, dx
tags: microsoft sw programming assembly hw
Q105: Write a program to find whether a given m/c is big-endian or little-endian!
tags: microsoft sw programming hw
Q147: What does the following code do? xor eax,eax mov ebx,data ; your input data mov cl,bits ; number of bits loop: ror ebx,1 rcl eax,1 dec cl jnz loop
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q148: Explain what is DMA?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q149: What is pipelining?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q150: What are superscalar machines and vliw machines?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q151: What is cache?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q152: What is cache coherency and how is it eliminated?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q153: What is write back and write through caches?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q154: What are different pipelining hazards and how are they eliminated.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q155: What are different stages of a pipe?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q156: Explain more about branch prediction in controlling the control hazards
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q157: Give examples of data hazards with pseudo codes.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q158: How do you calculate the number of sets given its way and size in a cache?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q159: How is a block found in a cache?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q160: Scoreboard analysis.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q161: What is miss penalty and give your own ideas to eliminate it.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q162: How do you improve the cache performance.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q163: Different addressing modes.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q164: Computer arithmetic with twos complements.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q165: About hardware and software interrupts.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q166: What is bus contention and how do you eliminate it.
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q167: What is aliasing?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q168: What is the difference between a latch and a flip flop?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q169: What is the race around condition? How can it be overcome?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q170: What is the purpose of cache? How is it used?
tags: microsoft intel amd nvidia hw comparch architecture hardware
Q171: What are the main issues associated with multiprocessor caches and how might you address them?
tags: Intel AMD nVidia ATI Sun HP hw architecture design
Q182: An 8bit ADC with parallel output converts input signal into digital numbers. You have to come up with the idea of a circuit, that finds the maxomum of every 10 numbers at the output of the ADC.
tags: Intel AMD nVidia ATI Sun HP hardware hw design circuit logic
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